1. Technical Field
This disclosure generally relates to semiconductor wafers, semiconductor-wafer-layout determining methods, and reticle-layout determining methods, and particularly relates to a semiconductor wafer having an alignment mark for positioning the wafer, a semiconductor-wafer layout determining method, and a reticle-layout determining method for implementing the semiconductor-wafer layout determining method.
2. Description of the Related Art
In the manufacturing of semiconductor devices having analog circuits, generally, laser trimming for adjusting resistance by cutting fuses is performed on the wafers in order to improve the analog characteristics of the semiconductor devices. An alignment mark is formed on a semiconductor wafer for the purpose of positioning the semiconductor wafer during such laser trimming process.
A plurality of device chip areas are arranged in matrix form on a semiconductor wafer, and are separated from each other by scribe lines. An alignment mark for use in laser trimming is provided separately for each of the device chip areas (see Patent Document 1, for example).
In the laser trimming process, an alignment mark is utilized to position the semiconductor wafer and align the angle (Θ).    [Patent Document 1] Japanese Patent Application Publication No. 2001-35924
In recent years, progress in the miniaturization of semiconductor devices has been made, resulting in the size of device chip areas being decreased. This makes it difficult to dispose an alignment mark in each device chip area.
Provision of an alignment mark in a device chip area means an increase in the size of the device chip area, resulting in a decrease in the number of device chip areas provided on a semiconductor wafer. This gives rise to a problem that the manufacturing cost increases.
Further, even if an alignment mark is arranged on a scribe line, the provision of alignment marks for respective device chip areas may create interference with other cells that are arranged on scribe lines. Because of this, there may be a situation where alignment marks cannot be disposed as desired. In such a case, the width of the scribe lines may need to be widened. This means an increase in the width of the scribe lines, resulting in a decrease in the number of device chip areas provided on a semiconductor wafer. This gives rise to a problem that the manufacturing cost increases.
Accordingly, there is a need for a semiconductor wafer, a semiconductor-wafer layout determining method, and a reticle-layout determining method for implementing the semiconductor-wafer layout determining method that can arrange alignment marks without enlarging device chip areas or widening the width of scribe lines.